A CCD based neural network integrated circuit with 64K analog programmable synapses

Aharon J. Agranat*, Charles F. Neugebauer, Amnon Yariv

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

10 Scopus citations

Abstract

A report is presented on the design, fabrication, and testing of a neural network integrated circuit with 65,536 analog programmable synapses (256 fully interconnected neurons). The integrated circuit utilizes charge-coupled devices (CCDs) based on a generic architecture that the authors proposed earlier. Preliminary testing of the CCD neural processor indicates that the operating speed is 0.5 × 109 analog interconnect updates/s. Loading of the synaptic interaction matrix can be accomplished either electrically or optically within 0.5 ms or 1 ms, respectively.

Original languageAmerican English
Pages551-555
Number of pages5
StatePublished - 1990
Externally publishedYes
Event1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3) - San Diego, CA, USA
Duration: 17 Jun 199021 Jun 1990

Conference

Conference1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3)
CitySan Diego, CA, USA
Period17/06/9021/06/90

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