A CCD based neural network integrated circuit with 64K analog programmable synapses

Aharon J. Agranat; Charles F. Neugebauer; Amnon Yariv

A CCD based neural network integrated circuit with 64K analog programmable synapses

Aharon J. Agranat^*, Charles F. Neugebauer, Amnon Yariv

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

11 Scopus citations

Abstract

A report is presented on the design, fabrication, and testing of a neural network integrated circuit with 65,536 analog programmable synapses (256 fully interconnected neurons). The integrated circuit utilizes charge-coupled devices (CCDs) based on a generic architecture that the authors proposed earlier. Preliminary testing of the CCD neural processor indicates that the operating speed is 0.5 × 10⁹ analog interconnect updates/s. Loading of the synaptic interaction matrix can be accomplished either electrically or optically within 0.5 ms or 1 ms, respectively.

Original language	English
Pages	551-555
Number of pages	5
State	Published - 1990
Externally published	Yes
Event	1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3) - San Diego, CA, USA Duration: 17 Jun 1990 → 21 Jun 1990

Conference

Conference	1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3)
City	San Diego, CA, USA
Period	17/06/90 → 21/06/90

Cite this

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title = "A CCD based neural network integrated circuit with 64K analog programmable synapses",

abstract = "A report is presented on the design, fabrication, and testing of a neural network integrated circuit with 65,536 analog programmable synapses (256 fully interconnected neurons). The integrated circuit utilizes charge-coupled devices (CCDs) based on a generic architecture that the authors proposed earlier. Preliminary testing of the CCD neural processor indicates that the operating speed is 0.5 × 109 analog interconnect updates/s. Loading of the synaptic interaction matrix can be accomplished either electrically or optically within 0.5 ms or 1 ms, respectively.",

author = "Agranat, \{Aharon J.\} and Neugebauer, \{Charles F.\} and Amnon Yariv",

year = "1990",

language = "אנגלית",

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note = "1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3) ; Conference date: 17-06-1990 Through 21-06-1990",

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AU - Agranat, Aharon J.

AU - Neugebauer, Charles F.

AU - Yariv, Amnon

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N2 - A report is presented on the design, fabrication, and testing of a neural network integrated circuit with 65,536 analog programmable synapses (256 fully interconnected neurons). The integrated circuit utilizes charge-coupled devices (CCDs) based on a generic architecture that the authors proposed earlier. Preliminary testing of the CCD neural processor indicates that the operating speed is 0.5 × 109 analog interconnect updates/s. Loading of the synaptic interaction matrix can be accomplished either electrically or optically within 0.5 ms or 1 ms, respectively.

AB - A report is presented on the design, fabrication, and testing of a neural network integrated circuit with 65,536 analog programmable synapses (256 fully interconnected neurons). The integrated circuit utilizes charge-coupled devices (CCDs) based on a generic architecture that the authors proposed earlier. Preliminary testing of the CCD neural processor indicates that the operating speed is 0.5 × 109 analog interconnect updates/s. Loading of the synaptic interaction matrix can be accomplished either electrically or optically within 0.5 ms or 1 ms, respectively.

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SP - 551

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T2 - 1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3)

Y2 - 17 June 1990 through 21 June 1990

ER -

A CCD based neural network integrated circuit with 64K analog programmable synapses

Abstract

Conference

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