Asymmetric Transistor Aging in Modern Accelerators: Reliability Challenges, Vulnerabilities, and Mitigation Strategies

Modern computing systems increasingly rely on hardware accelerators to satisfy the performance and energy-efficiency demands of artificial intelligence, high-performance computing, and cryptographic applications. As accelerators are rapidly deployed in mission-critical systems, their long-term reliability becomes a major concern. Unlike general-purpose processors, accelerators exhibit highly workload-dependent utilization patterns and rely heavily on power-management techniques such as clock gating, power gating, sparsity exploitation, and workload scheduling. These characteristics create non-uniform activity profiles that promote asymmetric transistor aging.This paper examines the reliability challenges posed by asymmetric aging in modern accelerators. Using graphics processing units (GPUs), systolic-array-based machine-learning accelerators, and cryptographic AES accelerators as representative case studies, we show how workload-dependent utilization, prolonged idle periods, thermal-density effects, and resource-allocation policies can produce significant aging imbalances across hardware resources. These imbalances lead to timing degradation, silent data corruption, functional failures, and, in some cases, security vulnerabilities. Finally, we discuss mitigation approaches including aging-aware scheduling, anti-aging agents, monitoring infrastructures, and aging-aware architectural design. Our analysis highlights that aging in accelerators differs fundamentally from that in general-purpose processors and argues that aging resilience must become a first-class design objective for future accelerator architectures.