Barrier synchronization on a loaded SMP using two-phase waiting algorithms

D. Tsafrir, D. G. Feitelson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Little work has been done on the performance of barrier synchronization using two-phase blocking, as the common wisdom is that it is useless to spin if the total number of threads in the system exceeds the number of processors. We challenge this and show that it may be beneficial to spin-wait even if the number of threads is up to double the number of processors, especially if the waiting time is at least twice the context switch overhead (rather than being equal to it). We also characterize the alternating synchronization pattern that applications based on barriers tend to fall into which is quite different from the patterns typically assumed in theoretical analyses.

Original languageAmerican English
Title of host publicationProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages755-762
Number of pages8
ISBN (Electronic)0769515738, 9780769515731
DOIs
StatePublished - 2002
Event16th International Parallel and Distributed Processing Symposium, IPDPS 2002 - Ft. Lauderdale, United States
Duration: 15 Apr 200219 Apr 2002

Publication series

NameProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002

Conference

Conference16th International Parallel and Distributed Processing Symposium, IPDPS 2002
Country/TerritoryUnited States
CityFt. Lauderdale
Period15/04/0219/04/02

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

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