Barrier synchronization on a loaded SMP using two-phase waiting algorithms

D. Tsafrir; D. G. Feitelson

doi:10.1109/IPDPS.2002.1015592

Barrier synchronization on a loaded SMP using two-phase waiting algorithms

D. Tsafrir, D. G. Feitelson

The Rachel and Selim Benin School of Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Little work has been done on the performance of barrier synchronization using two-phase blocking, as the common wisdom is that it is useless to spin if the total number of threads in the system exceeds the number of processors. We challenge this and show that it may be beneficial to spin-wait even if the number of threads is up to double the number of processors, especially if the waiting time is at least twice the context switch overhead (rather than being equal to it). We also characterize the alternating synchronization pattern that applications based on barriers tend to fall into which is quite different from the patterns typically assumed in theoretical analyses.

Original language	English
Title of host publication	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	755-762
Number of pages	8
ISBN (Electronic)	0769515738, 9780769515731
DOIs	https://doi.org/10.1109/IPDPS.2002.1015592
State	Published - 2002
Event	16th International Parallel and Distributed Processing Symposium, IPDPS 2002 - Ft. Lauderdale, United States Duration: 15 Apr 2002 → 19 Apr 2002

Publication series

Name	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002

Conference

Conference	16th International Parallel and Distributed Processing Symposium, IPDPS 2002
Country/Territory	United States
City	Ft. Lauderdale
Period	15/04/02 → 19/04/02

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

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10.1109/IPDPS.2002.1015592

Cite this

Tsafrir, D., & Feitelson, D. G. (2002). Barrier synchronization on a loaded SMP using two-phase waiting algorithms. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002 (pp. 755-762). Article 1015592 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPS.2002.1015592

@inproceedings{d4402b05fa00414688703aa962ea26e4,

title = "Barrier synchronization on a loaded SMP using two-phase waiting algorithms",

abstract = "Little work has been done on the performance of barrier synchronization using two-phase blocking, as the common wisdom is that it is useless to spin if the total number of threads in the system exceeds the number of processors. We challenge this and show that it may be beneficial to spin-wait even if the number of threads is up to double the number of processors, especially if the waiting time is at least twice the context switch overhead (rather than being equal to it). We also characterize the alternating synchronization pattern that applications based on barriers tend to fall into which is quite different from the patterns typically assumed in theoretical analyses.",

author = "D. Tsafrir and Feitelson, {D. G.}",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 16th International Parallel and Distributed Processing Symposium, IPDPS 2002 ; Conference date: 15-04-2002 Through 19-04-2002",

year = "2002",

doi = "10.1109/IPDPS.2002.1015592",

language = "אנגלית",

series = "Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "755--762",

booktitle = "Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002",

address = "ארצות הברית",

}

Tsafrir, D & Feitelson, DG 2002, Barrier synchronization on a loaded SMP using two-phase waiting algorithms. in Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002., 1015592, Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002, Institute of Electrical and Electronics Engineers Inc., pp. 755-762, 16th International Parallel and Distributed Processing Symposium, IPDPS 2002, Ft. Lauderdale, United States, 15/04/02. https://doi.org/10.1109/IPDPS.2002.1015592

Barrier synchronization on a loaded SMP using two-phase waiting algorithms. / Tsafrir, D.; Feitelson, D. G.
Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 755-762 1015592 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Barrier synchronization on a loaded SMP using two-phase waiting algorithms

AU - Tsafrir, D.

AU - Feitelson, D. G.

PY - 2002

Y1 - 2002

N2 - Little work has been done on the performance of barrier synchronization using two-phase blocking, as the common wisdom is that it is useless to spin if the total number of threads in the system exceeds the number of processors. We challenge this and show that it may be beneficial to spin-wait even if the number of threads is up to double the number of processors, especially if the waiting time is at least twice the context switch overhead (rather than being equal to it). We also characterize the alternating synchronization pattern that applications based on barriers tend to fall into which is quite different from the patterns typically assumed in theoretical analyses.

AB - Little work has been done on the performance of barrier synchronization using two-phase blocking, as the common wisdom is that it is useless to spin if the total number of threads in the system exceeds the number of processors. We challenge this and show that it may be beneficial to spin-wait even if the number of threads is up to double the number of processors, especially if the waiting time is at least twice the context switch overhead (rather than being equal to it). We also characterize the alternating synchronization pattern that applications based on barriers tend to fall into which is quite different from the patterns typically assumed in theoretical analyses.

UR - http://www.scopus.com/inward/record.url?scp=84966501437&partnerID=8YFLogxK

U2 - 10.1109/IPDPS.2002.1015592

DO - 10.1109/IPDPS.2002.1015592

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:84966501437

T3 - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002

SP - 755

EP - 762

BT - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th International Parallel and Distributed Processing Symposium, IPDPS 2002

Y2 - 15 April 2002 through 19 April 2002

ER -

Tsafrir D, Feitelson DG. Barrier synchronization on a loaded SMP using two-phase waiting algorithms. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 755-762. 1015592. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2002). doi: 10.1109/IPDPS.2002.1015592

Barrier synchronization on a loaded SMP using two-phase waiting algorithms

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