Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging

Keyphrases

• Clock Tree 100%
• Transistor Aging 100%
• Tree Layout 100%
• Bias Temperature Instability 50%
• Asymmetric Aging 50%
• Timing Violation 50%
• Reliability Issues 25%
• Time-dependent Reliability 25%
• Useful Skew 25%
• Gradual Deterioration 25%
• Degradation Performance 25%
• Integrated Circuit Reliability 25%
• Buffer Delay 25%
• Clock Buffer 25%
• Critical Circuit 25%
• Circuit Failure 25%

Computer Science

• Reliability Concern 66%
• And Gate 33%
• Clock Skew 33%

Engineering

• Reliability Issue 33%
• Design Flow 33%
• System Reliability 33%