Effect of high-temperature anneal on interface states generation in stressed metal-oxide-semiconductor devices

M. Berger*, E. Avni, J. Shappir

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

Polycrystalline silicon gate metal-oxide-semiconductor transistors, fabricated with polycrystalline silicon leads, were repeatedly electrically stressed by constant-current Fowler-Nordheim tunneling cycles. After every stress cycle the devices were annealed for various time intervals at 950°C. Capacitance-voltage measurements were used to detect stress-related interface-state generation rates and saturation values. It was found that although the stress-generated interface states are totally annealed by the thermal treatment, their generation rates and saturation values after anneal are a strong function of the anneal time, significantly exceeding the values of the fresh devices and inversely dependent on the anneal time. From the results it is concluded that a new type of latent interface-state sites is generated by the combination of tunneling stress and high-temperature annealing.

Original languageEnglish
Pages (from-to)598-600
Number of pages3
JournalApplied Physics Letters
Volume58
Issue number6
DOIs
StatePublished - 1991

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