Abstract
Value prediction attempts to eliminate true-data dependencies by dynamically predicting the outcome values of instructions and executing true-data dependent instructions based on that prediction. In this paper we attempt to understand the limitations of using this paradigm in realistic machines. We show that the instruction-fetch bandwidth and the issue rate have a very significant impact on the efficiency of value prediction. In addition, we study how recent techniques to improve the instruction-fetch rate affect the efficiency of value prediction and its hardware organization.
Original language | English |
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Pages (from-to) | 272-281 |
Number of pages | 10 |
Journal | Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA |
DOIs | |
State | Published - 1998 |
Externally published | Yes |
Event | Proceedings of the 1998 25th Annual International Symposium on Computer Architecture - Barcelona, Spain Duration: 27 Jun 1998 → 1 Jul 1998 |