Hardware-efficient quantum error correction via concatenated bosonic qubits

To solve problems of practical importance^1,2, quantum computers probably need to incorporate quantum error correction, in which a logical qubit is redundantly encoded in many noisy physical qubits^{3, 4–5}. The large physical-qubit overhead associated with error correction motivates the search for more hardware-efficient approaches^{6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17–18}. Here, using a superconducting quantum circuit¹⁹, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance d = 5 (ref. ¹⁰). A stabilizing circuit passively protects cat qubits against bit flips^{20, 21, 22, 23–24}. The repetition code, using ancilla transmons for syndrome measurement, corrects cat qubit phase flips. We study the performance and scaling of the logical qubit memory, finding that the phase-flip correcting repetition code operates below the threshold. The logical bit-flip error is suppressed with increasing cat qubit mean photon number, enabled by our realization of a cat-transmon noise-biased CX gate. The minimum measured logical error per cycle is on average 1.75(2)% for the distance-3 code sections, and 1.65(3)% for the distance-5 code. Despite the increased number of fault locations of the distance-5 code, the high degree of noise bias preserved during error correction enables comparable performance. These results, where the intrinsic error suppression of the bosonic encodings enables us to use a hardware-efficient outer error-correcting code, indicate that concatenated bosonic codes can be a compelling model for reaching fault-tolerant quantum computation.