HIGH-PERFORMANCE MOS TECHNOLOGY FOR 16K STATIC RAM.

S. S. Liu; R. J. Smith; R. D. Pashley; J. Shappir; C. H. Fu; K. R. Kokkonen

HIGH-PERFORMANCE MOS TECHNOLOGY FOR 16K STATIC RAM.

S. S. Liu^*, R. J. Smith, R. D. Pashley, J. Shappir, C. H. Fu, K. R. Kokkonen

^*Corresponding author for this work

The Rachel and Selim Benin School of Engineering and Computer Science

Research output: Contribution to conference › Paper › peer-review

7 Scopus citations

Abstract

A scaled double-poly MOS technology has been developed which features a static memory cell size of 1. 5 mil**2 with 4 mu design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 400 A and poly-Si channel length to 2. 1 mu with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.

Original language	English
Pages	352-354
Number of pages	3
State	Published - 1979
Event	Int Electron Devices Meet, 25th, Tech Dig - Washington, DC, USA Duration: 3 Dec 1979 → 5 Dec 1979

Conference

Conference	Int Electron Devices Meet, 25th, Tech Dig
City	Washington, DC, USA
Period	3/12/79 → 5/12/79

Cite this

@conference{db49db1a6fa440cebe88635bd8254bd7,

title = "HIGH-PERFORMANCE MOS TECHNOLOGY FOR 16K STATIC RAM.",

abstract = "A scaled double-poly MOS technology has been developed which features a static memory cell size of 1. 5 mil**2 with 4 mu design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 400 A and poly-Si channel length to 2. 1 mu with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.",

author = "Liu, {S. S.} and Smith, {R. J.} and Pashley, {R. D.} and J. Shappir and Fu, {C. H.} and Kokkonen, {K. R.}",

year = "1979",

language = "אנגלית",

pages = "352--354",

note = "Int Electron Devices Meet, 25th, Tech Dig ; Conference date: 03-12-1979 Through 05-12-1979",

}

TY - CONF

T1 - HIGH-PERFORMANCE MOS TECHNOLOGY FOR 16K STATIC RAM.

AU - Liu, S. S.

AU - Smith, R. J.

AU - Pashley, R. D.

AU - Shappir, J.

AU - Fu, C. H.

AU - Kokkonen, K. R.

PY - 1979

Y1 - 1979

N2 - A scaled double-poly MOS technology has been developed which features a static memory cell size of 1. 5 mil**2 with 4 mu design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 400 A and poly-Si channel length to 2. 1 mu with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.

AB - A scaled double-poly MOS technology has been developed which features a static memory cell size of 1. 5 mil**2 with 4 mu design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 400 A and poly-Si channel length to 2. 1 mu with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.

UR - http://www.scopus.com/inward/record.url?scp=0018705044&partnerID=8YFLogxK

M3 - ???researchoutput.researchoutputtypes.contributiontoconference.paper???

AN - SCOPUS:0018705044

SP - 352

EP - 354

T2 - Int Electron Devices Meet, 25th, Tech Dig

Y2 - 3 December 1979 through 5 December 1979

ER -

HIGH-PERFORMANCE MOS TECHNOLOGY FOR 16K STATIC RAM.

Abstract

Conference

Other files and links

Fingerprint

Cite this