With the integration of SMT solvers into analysis frameworks aimed at ensuring a system's end-to-end correctness, having a high level of confidence in these solvers' results has become crucial. For unsatisfiable queries, a reasonable approach is to have the solver return an independently checkable proof of unsatisfiability. We propose a lazy, extensible and robust method for enhancing DPLL(T)-style SMT solvers with proof-generation capabilities. Our method maintains separate Boolean-level and theory-level proofs, and weaves them together into one coherent artifact. Each theory-specific solver is called upon lazily, a posteriori, to prove precisely those solution steps it is responsible for and that are needed for the final proof. We present an implementation of our technique in the CVC4 SMT solver, capable of producing unsatisfiability proofs for quantifier-free queries involving uninterpreted functions, arrays, bitvectors and combinations thereof. We discuss an evaluation of our tool using industrial benchmarks and benchmarks from the SMT-LIB library, which shows promising results.
|Original language||American English|
|Title of host publication||Proceedings of the 16th Conference on Formal Methods in Computer-Aided Design, FMCAD 2016|
|Editors||Ruzica Piskac, Muralidhar Talupur|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||8|
|State||Published - 24 Mar 2017|
|Event||16th Conference on Formal Methods in Computer-Aided Design, FMCAD 2016 - Mountain View, United States|
Duration: 3 Oct 2016 → 6 Oct 2016
|Name||Proceedings of the 16th Conference on Formal Methods in Computer-Aided Design, FMCAD 2016|
|Conference||16th Conference on Formal Methods in Computer-Aided Design, FMCAD 2016|
|Period||3/10/16 → 6/10/16|
Bibliographical notePublisher Copyright:
© 2016 FMCAD Inc.