TY - JOUR
T1 - New generic approach for optoelectronic hardware realizations of neural networks models
AU - Agranat, Aharon
AU - Neugebauer, Charles F.
AU - Yariv, Amnon
PY - 1988
Y1 - 1988
N2 - A new generic approach for realizing neural networks (NN) is presented. The underlying principle of the new approach is to take advantage of the fact that signal processing in silicon is an advanced and mature technology, and to incorporate optics where silicon fails, namely, in the interconnectivity problems. The system consists of two main subassemblies: a 2D spatial light modulator (SLM) and an integrated circuit called the Neural Processor (NP). The synaptic efficacies matrix W is stored in the SLM. Thus by imaging the SLM contents onto an array detector which serves as the input unit of the NP, W is loaded in parallel into the NP. The NP then updates the state of the network in parallel/semiparallel-synchronous/asynchronous manner (depending on the structure of the NP). There are three distinct architectures for the NP: (a) a semiparallel synchronous NP based on CCD (charge coupled device) technology; (b) a fully parallel synchronous NP based on CID (charge injection device) technology; and (c) a fully parallel asynchronous NP with continuous updating of the neurons.
AB - A new generic approach for realizing neural networks (NN) is presented. The underlying principle of the new approach is to take advantage of the fact that signal processing in silicon is an advanced and mature technology, and to incorporate optics where silicon fails, namely, in the interconnectivity problems. The system consists of two main subassemblies: a 2D spatial light modulator (SLM) and an integrated circuit called the Neural Processor (NP). The synaptic efficacies matrix W is stored in the SLM. Thus by imaging the SLM contents onto an array detector which serves as the input unit of the NP, W is loaded in parallel into the NP. The NP then updates the state of the network in parallel/semiparallel-synchronous/asynchronous manner (depending on the structure of the NP). There are three distinct architectures for the NP: (a) a semiparallel synchronous NP based on CCD (charge coupled device) technology; (b) a fully parallel synchronous NP based on CID (charge injection device) technology; and (c) a fully parallel asynchronous NP with continuous updating of the neurons.
UR - http://www.scopus.com/inward/record.url?scp=0024171333&partnerID=8YFLogxK
U2 - 10.1016/0893-6080(88)90397-8
DO - 10.1016/0893-6080(88)90397-8
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AN - SCOPUS:0024171333
SN - 0893-6080
VL - 1
SP - 371
JO - Neural Networks
JF - Neural Networks
IS - 1 SUPPL
T2 - International Neural Network Society 1988 First Annual Meeting
Y2 - 6 September 1988 through 10 September 1988
ER -