TY - GEN
T1 - One algorithm to match them all
T2 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
AU - Weinsberg, Yaron
AU - Tzur-David, Shimrit
AU - Dolev, Danny
AU - Anker, Tal
PY - 2007
Y1 - 2007
N2 - Today's Network Intrusion Prevention Systems (NIPS) provide an important defense mechanism against security threats. The detection of network attacks utilizes a high-speed pattern matching algorithm that can be implemented in either hardware or software. Adapting a software-based pattern matching algorithm to hardware-based device is a complicated task. This paper presents a cost effective multi-pattern matching algorithm based on Field Programmable Gate Arrays (FPGAs) and standard RAM. The algorithm achieves line-rate speed, which is several orders of magnitude faster than the current state of the art, while attaining similar accuracy of detection. The algorithm can be easily adapted to operate in hardware-based NIPS and attain even higher speed by utilizing a TCAM memory.
AB - Today's Network Intrusion Prevention Systems (NIPS) provide an important defense mechanism against security threats. The detection of network attacks utilizes a high-speed pattern matching algorithm that can be implemented in either hardware or software. Adapting a software-based pattern matching algorithm to hardware-based device is a complicated task. This paper presents a cost effective multi-pattern matching algorithm based on Field Programmable Gate Arrays (FPGAs) and standard RAM. The algorithm achieves line-rate speed, which is several orders of magnitude faster than the current state of the art, while attaining similar accuracy of detection. The algorithm can be easily adapted to operate in hardware-based NIPS and attain even higher speed by utilizing a TCAM memory.
UR - http://www.scopus.com/inward/record.url?scp=47649104471&partnerID=8YFLogxK
U2 - 10.1109/HPSR.2007.4281234
DO - 10.1109/HPSR.2007.4281234
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AN - SCOPUS:47649104471
SN - 1424412064
SN - 9781424412068
T3 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
SP - 252
EP - 257
BT - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
Y2 - 30 May 2007 through 1 June 2007
ER -