Packet-mode emulation of output-queued switches

Hagit Attiya*, David Hay, Isaac Keslassy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Most common network protocols (e.g., the Internet Protocol) work with variable size packets, whereas contemporary switches still operate with fixed size cells, which are easier to transmit and buffer. This necessitates packet segmentation and reassembly modules, resulting in significant computation and communication overhead that might be too costly as switches become faster and bigger. It is therefore imperative to investigate an alternative mode of scheduling, in which packets are scheduled contiguously over the switch fabric. This paper investigates the cost of packet-mode scheduling for the combined input output queued (CIOQ) switch architecture. We devise frame-based schedulers that allow a packetmode CIOQ switch with small speedup to mimic an ideal output-queued switch with bounded relative queuing delay. The schedulers are pipelined and are based on matrix de-composition. Our schedulers demonstrate a trade-off between the switch speedup and the relative queuing delay incurred while mimicking an output-queued switch. When the switch is allowed to incur high relative queuing delay, a speedup arbitrarily close to 2 suffices to mimic an ideal output-queued switch. This implies that packet-mode scheduling does not require higher speedup than a cell-based scheduler. The relative queuing delay can be significantly reduced with just a doubling of the speedup. We further show that it is impossible to achieve zero relative queuing delay (that is, a perfect emulation), regardless of the switch speedup. Finally, we show that a speedup arbitrarily close to 1 suffices to mimic an output-queued switch with a bounded buffer size.

Original languageAmerican English
Title of host publicationSPAA 2006
Subtitle of host publication18th Annual ACM Symposium on Parallelism in Algorithms and Architectures
PublisherAssociation for Computing Machinery (ACM)
Pages138-147
Number of pages10
ISBN (Print)1595934529, 9781595934529
DOIs
StatePublished - 2006
Externally publishedYes
EventSPAA 2006: 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures - Cambridge, MA, United States
Duration: 30 Jul 20062 Aug 2006

Publication series

NameAnnual ACM Symposium on Parallelism in Algorithms and Architectures
Volume2006

Conference

ConferenceSPAA 2006: 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures
Country/TerritoryUnited States
CityCambridge, MA
Period30/07/062/08/06

Keywords

  • CIOQ Switch
  • Output-Queued Switch Emulation
  • Packet switching
  • Packet-Mode Scheduling
  • Queuing delay

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