PARALLEL ALGORITHMS FOR CHIP PLACEMENT BY SIMULATED ANNEALING.

F. Darema; S. Kirkpatrick; V. A. Norton

doi:10.1147/rd.313.0391

PARALLEL ALGORITHMS FOR CHIP PLACEMENT BY SIMULATED ANNEALING.

F. Darema^*
, S. Kirkpatrick
, V. A. Norton

^*Corresponding author for this work

The Rachel and Selim Benin School of Engineering and Computer Science

Research output: Contribution to journal › Article › peer-review

49 Scopus citations

Abstract

We explore modifications to the standard simulated annealing method for circuit placement which make it more suitable for use on a shared-memory parallel computer. By employing chaotic approaches we allow the parallel algorithms to deviate from the algorithm defined for a serial computer and thus obtain good execution efficiencies for large numbers of processors. The qualitative behavior of the parallel algorithms is comparable to that of the serial algorithm.

Original language	English
Pages (from-to)	391-402
Number of pages	12
Journal	IBM Journal of Research and Development
Volume	31
Issue number	3
DOIs	https://doi.org/10.1147/rd.313.0391
State	Published - 1987

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AB - We explore modifications to the standard simulated annealing method for circuit placement which make it more suitable for use on a shared-memory parallel computer. By employing chaotic approaches we allow the parallel algorithms to deviate from the algorithm defined for a serial computer and thus obtain good execution efficiencies for large numbers of processors. The qualitative behavior of the parallel algorithms is comparable to that of the serial algorithm.

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PARALLEL ALGORITHMS FOR CHIP PLACEMENT BY SIMULATED ANNEALING.

Abstract

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