PARALLEL TECHNIQUES FOR CHIP PLACEMENT BY SIMULATED ANNEALING ON SHARED MEMORY SYSTEMS.

F. Darema; S. Kirkpatrick; V. A. Norton

PARALLEL TECHNIQUES FOR CHIP PLACEMENT BY SIMULATED ANNEALING ON SHARED MEMORY SYSTEMS.

F. Darema^*
, S. Kirkpatrick
, V. A. Norton

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

The authors investigate modifications on the standard simulated annealing method for circuit placement that are intended to make it more suitable for shared-memory highly parallel computers. By permitting temporary errors and using chaotic approaches they allow the parallel algorithms to deviate from the algorithm as defined for a serial computer and obtain good execution efficiencies for large numbers of processors. They find that the qualitative behavior of the parallel algorithms is comparable to the serial algorithm.

Original language	English
Title of host publication	Unknown Host Publication Title
Publisher	IEEE
Pages	87-90
Number of pages	4
ISBN (Print)	0818608021
State	Published - 1987
Externally published	Yes

Cite this

@inproceedings{2634a5f763734f30b34dc659ecb2e123,

title = "PARALLEL TECHNIQUES FOR CHIP PLACEMENT BY SIMULATED ANNEALING ON SHARED MEMORY SYSTEMS.",

abstract = "The authors investigate modifications on the standard simulated annealing method for circuit placement that are intended to make it more suitable for shared-memory highly parallel computers. By permitting temporary errors and using chaotic approaches they allow the parallel algorithms to deviate from the algorithm as defined for a serial computer and obtain good execution efficiencies for large numbers of processors. They find that the qualitative behavior of the parallel algorithms is comparable to the serial algorithm.",

author = "F. Darema and S. Kirkpatrick and Norton, \{V. A.\}",

year = "1987",

language = "אנגלית",

isbn = "0818608021",

publisher = "IEEE",

pages = "87--90",

booktitle = "Unknown Host Publication Title",

}

TY - GEN

T1 - PARALLEL TECHNIQUES FOR CHIP PLACEMENT BY SIMULATED ANNEALING ON SHARED MEMORY SYSTEMS.

AU - Darema, F.

AU - Kirkpatrick, S.

AU - Norton, V. A.

PY - 1987

Y1 - 1987

N2 - The authors investigate modifications on the standard simulated annealing method for circuit placement that are intended to make it more suitable for shared-memory highly parallel computers. By permitting temporary errors and using chaotic approaches they allow the parallel algorithms to deviate from the algorithm as defined for a serial computer and obtain good execution efficiencies for large numbers of processors. They find that the qualitative behavior of the parallel algorithms is comparable to the serial algorithm.

AB - The authors investigate modifications on the standard simulated annealing method for circuit placement that are intended to make it more suitable for shared-memory highly parallel computers. By permitting temporary errors and using chaotic approaches they allow the parallel algorithms to deviate from the algorithm as defined for a serial computer and obtain good execution efficiencies for large numbers of processors. They find that the qualitative behavior of the parallel algorithms is comparable to the serial algorithm.

UR - https://www.scopus.com/pages/publications/0023532206

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:0023532206

SN - 0818608021

SP - 87

EP - 90

BT - Unknown Host Publication Title

PB - IEEE

ER -

PARALLEL TECHNIQUES FOR CHIP PLACEMENT BY SIMULATED ANNEALING ON SHARED MEMORY SYSTEMS.

Abstract

Other files and links

Fingerprint

Cite this