Reducing the Temperature of Conventional Silicon Epitaxy for Selective Poly-Epi Growth

Silicon epitaxy and selective poly-epi growth (SPEG) were performed in a conventional epitaxy system at temperatures below 1000°C using a silane source in hydrogen ambient. Characterization methods included secondary ion mass spectrometry, transmission electron microscopy (TEM), scanning electron microscopy, and electrical measurements. Epitaxial silicon layers with good quality were obtained for both uniform and SPEG wafers at temperatures as low as 850°C. A strong correlation between the electrical results and the interfacial oxygen concentrations was obtained. The electrical results degrade while the interfacial oxygen concentration increases as the bake and deposition temperatures are reduced. This is attributed to inefficient removal of the native oxide. Nevertheless, the presence of relatively small precipitates of silicon oxide seen by TEM may still permit growth of an epitaxial layer with good electrical quality. The epitaxial layer was found to be about 50% thicker than the poly layer deposited over the oxide. This is explained by the smaller sticking coefficient of silicon to oxide as compared to that of silicon to silicon. This difference in layer thickness results in the formation of facets at the transition region between poly and epi.