TY - JOUR
T1 - Reduction of Depth of Boolean Networks with a Fan-In Constraint
AU - Preparata, Franco P.
AU - Muller, David E.
AU - Barak, Amnon B.
PY - 1977/5
Y1 - 1977/5
N2 - In this paper we present a family of techniques for the design of combinational networks whose objective is the reduction of the number of levels, subject to a constraint on the fan-in of the logic gates. We show that a Boolean expression with n literals and involving the connectives AND and OR can be restructured so that the resulting network of AND and OR gates has depth at most Cl log2 n + δ, where δ < 0.415 and Cl is 1.81, 1.38, 1.18, and 1 for maximum fan-in l of 2, 3, 4, and 5, respectively. If we additionally require that the amount of equipment of the resulting network be bounded by a linear function of n, it is possible to bound the depth by 2 log2 n with a fan-in of at most 3.
AB - In this paper we present a family of techniques for the design of combinational networks whose objective is the reduction of the number of levels, subject to a constraint on the fan-in of the logic gates. We show that a Boolean expression with n literals and involving the connectives AND and OR can be restructured so that the resulting network of AND and OR gates has depth at most Cl log2 n + δ, where δ < 0.415 and Cl is 1.81, 1.38, 1.18, and 1 for maximum fan-in l of 2, 3, 4, and 5, respectively. If we additionally require that the amount of equipment of the resulting network be bounded by a linear function of n, it is possible to bound the depth by 2 log2 n with a fan-in of at most 3.
KW - Boolean expressions
KW - combinational networks
KW - computational complexity
KW - design algorithms
KW - fan-in
KW - network depth
KW - number of levels
KW - parallel computation
UR - http://www.scopus.com/inward/record.url?scp=0017495649&partnerID=8YFLogxK
U2 - 10.1109/TC.1977.1674864
DO - 10.1109/TC.1977.1674864
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AN - SCOPUS:0017495649
SN - 0018-9340
VL - C-26
SP - 474
EP - 479
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
IS - 5
ER -