RISC-V and SHA-256 Accelerator Hackathon: A Problem-Based Learning Approach to Hardware-Software Co-Design

Hackathons have emerged as a powerful Problem-Based Learning (PBL) approach in engineering education, fostering active engagement, teamwork, and problem-solving under real-world constraints. This paper presents an educational hackathon in which students designed a RISC-V core based on the Imagination University Program and a SHA-256 cryptographic accelerator, implemented on a Xilinx Nexys A7-100T FPGA board. The hackathon was integrated into a VLSI course with three preparatory workshops - focused on FPGA setup, accelerator interfacing, and software co-design - culminating in a final open-ended challenge. The goals of the hackathon were fourfold: (1) apply PBL in hardware/software co-design, (2) enhance practical FPGA and RISC-V skills, (3) develop collaboration and creativity under time constraints, and (4) increase motivation toward VLSI careers. Survey results revealed increased motivation, enhanced technical and collaborative skills, and strengthened career interest. This work demonstrates the value of hackathons as a PBL methodology for advancing practical skills and professional readiness in computer engineering education.