Sharing memory robustly in message-passing systems

Emulators that translate algorithms from the shared-memory model to two different message-passing models are presented. Both are achieved by implementing a wait-free, atomic, single-writer multi-reader register in unreliable, asynchronous networks. The two message-passing models considered are a complete network with processor failures and an arbitrary network with dynamic link failures. These results make it possible to view the shared-memory model as a higher-level language for designing algorithms in asynchronous distributed systems. Any wait-free algorithn based on atomic, single-writer multi-reader registers can be automatically emulated in message-passing systems. The over-head introduced by these emulations is polynomial in the number of processors in the systems. Immediate new results are obtained by applying the emulators to known shared-memory algorithms.