Abstract
A generic architecture for realizing neural networks is presented in which the synaptic interaction matrix is loaded in parallel into an electronic integrated circuit from a SLM. Three types of the electronic processors are described using CCD, CID and CMOS technologies respectively. The pros and cons of currently existing SLMs for this architecture are pointed out.
| Original language | English |
|---|---|
| Pages (from-to) | 177-191 |
| Number of pages | 15 |
| Journal | Proceedings of SPIE - The International Society for Optical Engineering |
| Volume | 1150 |
| DOIs | |
| State | Published - 22 May 1990 |
| Externally published | Yes |