The inherent queuing delay of parallel packet switches

Hagit Attiya*, David Hay

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The parallel packet switch (PPS) is extensively used as the core of contemporary commercial switches. This paper investigates the inherent queuing delay and delay jitter introduced by the PPS's demultiplexing algorithm, relative to an optimal work-conserving switch. We show that the inherent queuing delay and delay jitter of a symmetric and fault-tolerant N × N PPS, where every demultiplexing algorithm dispatches cells to all the middle-stage switches is Ω(N), if there are no buffers in the PPS input-ports. If the demultiplexing algorithms dispatch cells only to part of the middle-stage switches, the queuing delay and delay jitter are Ω (N/S), where S is the PPS speedup. These lower bounds hold unless the demultiplexing algorithm has full and immediate knowledge of the switch status. When the PPS has buffers in its input-ports, Ω(N/S) an lower bound holds if the demultiplexing algorithm uses only local information, or the input buffers are small relative to the time an input-port needs to learn the switch global information.

Original languageAmerican English
Title of host publicationExploring New Frontiers of Theoretical Informatics - IFIP 18th World Computer Congress TC1 and 3rd International Conference on Theoretical Computer Science, TCS 2004
PublisherSpringer New York LLC
Pages139-152
Number of pages14
ISBN (Print)1402081405, 9781402081408
DOIs
StatePublished - 2004
Externally publishedYes
EventIFIP 18th World Computer Congress, TC1 and 3rd International Conference on Theoretical Computer Science, TCS 2004 - Toulouse, France
Duration: 22 Aug 200427 Aug 2004

Publication series

NameIFIP Advances in Information and Communication Technology
Volume155
ISSN (Print)1868-4238

Conference

ConferenceIFIP 18th World Computer Congress, TC1 and 3rd International Conference on Theoretical Computer Science, TCS 2004
Country/TerritoryFrance
CityToulouse
Period22/08/0427/08/04

Keywords

  • Clos networks
  • Delay jitter
  • Inverse multiplexing
  • Leaky-bucket traffic
  • Load balancing
  • Packet switching
  • Queuing delay

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