The inherent queuing delay of parallel packet switches

Hagit Attiya*, David Hay

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The parallel packet switch (PPS) extends the inverse multiplexing architecture and is widely used as the core of contemporary commercial switches. This paper investigates the inherent queuing delay introduced by the PPS's demultiplexing algorithm, responsible for dispatching cells to the middle-stage switches, relative to an optimal work-conserving switch. We first consider an N × N PPS without buffers in its input ports, operating at external rate R, internal rate r<R, and speedup (or overcapacity) S. We show that the inherent queuing delay of a symmetric and fault-tolerant PPS, where every demultiplexor may dispatch cells to all middle-stage switches, is Ω (N R/r) if no information is shared between the input ports. Sharing information between the input ports significantly reduces this lower bound, even if the information is outdated. These lower bounds indicate that employing algorithms using slightly out-of-date information may greatly improve the PPS performance. When the PPS has buffers in its input ports, an Ω(N/S) lower bound holds if the demultiplexing algorithm uses only local information or the input buffers are small relative to the time an input port needs to learn the switch global information.

Original languageAmerican English
Pages (from-to)1037-1047
Number of pages11
JournalIEEE Transactions on Parallel and Distributed Systems
Volume17
Issue number9
DOIs
StatePublished - Sep 2006
Externally publishedYes

Keywords

  • ATM
  • Internetworking
  • Packet-switching networks

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