The inherent queuing delay of parallel packet switches

Hagit Attiya*, David Hay

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

The parallel packet switch (PPS) is extensively used as the core of contemporary commercial switches. This paper investigates the inherent queuing delay and delay jitter introduced by the PPS's demultiplexing algorithm, relative to an optimal work-conserving switch. We show that the inherent queuing delay and delay jitter of a symmetric and fault-tolerant N × N PPS, where every demultiplexing algorithm dispatches cells to all the middle-stage switches is Ω(N), if there are no buffers in the PPS input-ports. If the demultiplexing algorithms dispatch cells only to part of the middle-stage switches, the queuing delay and delay jitter are Ω(N/S), where 5 is the PPS speedup. These lower bounds hold unless the demultiplexing algorithm has full and immediate knowledge of the switch status. When the PPS has buffers in its input-ports, an Ω(N/S) lower bound holds if the demultiplexing algorithm uses only local information, or the input buffers are small relative to the time an input-port needs to learn the switch global information.

Original languageAmerican English
Pages269-270
Number of pages2
DOIs
StatePublished - 2004
Externally publishedYes
EventSPAA 2004 - Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures - Barcelona, Spain
Duration: 27 Jun 200430 Jun 2004

Conference

ConferenceSPAA 2004 - Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures
Country/TerritorySpain
CityBarcelona
Period27/06/0430/06/04

Keywords

  • Clos networks
  • Delay jitter
  • Inverse multiplexing
  • Leaky-bucket traffic
  • Load balancing
  • Packet switching
  • Queuing delay

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