When AI Designs AI Hardware: Reliability Lessons from Accelerator Architectures

Large language models (LLMs) are no longer limited to serving as software coding assistants. Recent work has explored translating design specifications and block-level functionality into synthesizable Verilog, while newer agentic systems attempt to extend this capability across increasingly larger portions of the hardware design flow, from specification and RTL generation through verification, physical design, and GDS generation. These approaches are attractive because they promise shorter development cycles and faster architectural exploration. Although conventional physical-design quality-of-results (QoR) metrics are often reported, reliability considerations remain largely outside the scope of such flows.This omission is particularly concerning for modern accelerators, whose dense datapaths, large memories, high switching activity, aggressive clock targets, and low-voltage operation make reliability a first-order design constraint. Aging-induced degradation, timing and voltage margins, IR drop, electromigration, and thermal effects interact across architecture, RTL design, synthesis, place-and-route, and signoff. Consequently, reliability depends on preserving context across abstraction layers rather than optimizing individual implementation stages in isolation. This paper discusses reliability pitfalls that can arise when LLM-driven accelerator design systems prioritize local correctness or stage-specific optimization while failing to maintain the cross-stage reasoning required for reliable silicon.